PLX to explore 10GBase-T enhancements at Ethernet Summit

Company’s Teranetics 10GBase-T PHY division will present on 10GBase-T third-generation enhancements.

SUNNYVALE, Calif. -- PLX Technology, Inc. (NASDAQ: PLXT) announced that Jose Tellado, PLX vice president of systems engineering in the company’s Teranetics 10GBase-T PHY division, will present on 10GBase-T third-generation enhancements, at the upcoming Ethernet Technology Summit, at the Santa Marriott Hotel, Santa Clara, Calif., Wednesday, Feb. 23, 2:00 p.m. (PST).

Tellado will take part in the conference’s panel focused on Ethernet chipsets and components. His presentation, titled 10GBase-T Third Generation Enhancements, Enhanced Electromechanical Immunity, Energy-Efficient Ethernet, will address the interaction between external electromagnetic interference (EMI) and the operation of 10GBase-T links, as well as discuss available techniques for mitigating EMI. Additionally, the presentation will cover the Energy Efficient Ethernet (EEE) initiative and its integration into current 10GBase-T physical-layer (PHY) devices. Registration for this open session is free.

RELATED NEWS: PCIe house PLX acquires 10GBase-T PHY specialist Teranetics

“10GBase-T’s speed and compatibility with existing cabling structures are central to the technology’s further expansion into data centers and other enterprise applications,” said Lisa Huff, chief technology analyst at Discerning Analytics, and author of several reports covering high-speed networking solutions. “Providers of 10GBase-T silicon -- particularly those such as PLX who are designing PHYs at 40 nanometers -- are in a favorable position to capitalize on this growth.”

10GBase-T Aimed to Accelerate

Explosive growth is expected in 10GBase-T over next three years, with more than 22 million ports projected by 2014 (source: The Linley Group). As the recognized expert and market leader (more than 60 percent share) in 10GBase-T PHYs, PLX has delivered, through its Teranetics portfolio, the industry's first fully integrated chip implementation of single-, dual- and quad-port 10GBase-T PHYs. PLX products designed on 40nm process are sampling today.

10GBase-T technology enables increased bandwidth and speed over the existing standard, structured copper infrastructure. 10GBase-T PHY devices proliferate from basic aggregation ports for switch uplinks to single- and dual-port adapter cards for server applications to high-end, dense 24- and 48-port capacity 10GBase-T switches in data center applications. In each of these applications, PLX 10GBase-T PHYs offer ideal, optimally integrated solutions.

Presentation Abstract

Structured twisted pair cabling has been the workhorse of the local-area network for more than 20 years. A progression of standards, from Gigabit Ethernet to 10GBase-T, has taken the Ethernet PHY from simple two-level signaling to a highly sophisticated communication link using Tomlinson-Harashima Precoding (THP), full-matrix crosstalk cancellation and low density parity check (LDPC)-based forward error correction (FEC). With each progression in speed and as the operating speed inches closer to the capacity offered by twisted pair media, the industry has had to use more sophisticated tools from the communications theory toolbox to handle the reduced margin. With 10GBase-T moving from being “close to impossible” to widely available, and its complexity encapsulated in dual- and quad-port transceivers, there is increased concern about its vulnerability to EMI.

Information on the Ethernet technology Summit can be found at www.ethernetsummit.com.

PLX company and product information is available at www.plxtech.com.

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